Control and acquisition ASIC for imaging arrays. 5-channel parallel analog voltage input with CSA and 12-bit ADC in every channel, 8-channel parallel digital input, 40-channel parallel 3.3 V digital output for generation of arbitrary clock patterns. Integrated RAM memories for instructions and clock patterns. Integrated 3.3 V and 1.8 V LDOs for regulation of ROIC power and 16 integrated DACs for bias and reference voltage generation. The ASIC contains a programmable sequencer for generation of clock patterns and control of ASIC functions. SPI interface for ASIC control and 300 Mbps 8b/10b output data interface. Designed for use in cryogenic applications. Radiation hardened by design.

 

Keywords: ADC, Focal Plane Electronics, Cryogenic application, controller, IR