The IDE3160 (previously VATA160) is an application specific integrated circuit (ASIC), which has been designed for the front-end readout of photomultiplier tubes coupled to scintillators. The chip has 32 charge sensitive pre-amplifiers (CSA) inputs, a multiplexed output for the pulse heights, and a trigger output. The amplifiers are optimized for positive input charge in the range from -5pC to +13pC, but it can also be used with negative input charge. In each channel, the charge sensitive pre-amplifier is connected to a slow shaper that has nominally 2-μs shaping time and a fast shaper of 100-ns shaping time. The equivalent noise charge at the pulse height output is 3200e without load, and 4000e at 220pF input load for a readout clock speed of less than 500kHz. The pulse height integral non-linearity (INL) is 2% for positive charge. Each fast shaper output is connected to a comparator, which triggers when the pulse height exceeds the threshold level. The threshold can be adjusted externally for all channels in common, and trimmed for each channel using threshold trim 3-bit DACs. The minimum threshold above noise is +20fC. The comparator outputs are connected by logic OR, which provides a trigger signal that can be used by the external system to initiate the readout of the pulse heights of the slow shapers. The chip requires positive and negative supply voltages (-2.5V, +2.5V) and generates all bias currents internally. However, one can also apply bias currents externally, if needed. The total power is 181mW in steady state and 203mW maximum, depending on the readout rate. The chip has a 165-bit configuration register that allows one to program various features, and allows one to test and measure its gain by injection of an external calibrated charge. All amplifier inputs are protected by diodes against over-voltage and electro-static discharge (ESD).

 

Keywords: Photomultiplier tubes